Flash memory devices are classified into NOR type and NAND type devices. The NAND flash memory device is advantageous in that it has a high level of integration compared to the NOR flash memory device. A memory cell array of the NAND flash memory device includes a plurality of memory cell blocks. The memory cell block is described in more detail below.
FIG. 1 is a circuit diagram illustrating a memory cell block of a NAND flash memory device.
Referring to FIG. 1, a memory cell block includes a plurality of cell strings ST. The cell strings are respectively connected to bit lines BL1 to BL3 (only three bit lines are shown).
Each cell string ST has a structure in which a drain select transistor DST, a plurality of memory cells C0-1, C1 to Cn (n is an integer), and a source select transistor SST are connected in series. The drain select transistor DST included in each cell string has a drain connected to a corresponding bit line BL1, and the source select transistor SST has a source connected to a common source line CSL. The gates of the drain select transistors DST included in the respective cell strings are interconnected and become a drain select line DSL. Similarly, the gates of the source select transistors SST included in the respective cell strings are interconnected and become a source select line SSL. Further, the gates of the memory cells are interconnected and thus become word lines WL0 to WLn.
The memory cells C0-1 C0-2, and C0-3 sharing one word line (for example, WL0) are defined as one page Page0.
A program operation is performed in order to store data in the flash memory cell. The program operation is performed on per page basis. In the program operation, a program voltage of 15V or more is applied to a selected word line (for example, WL0), and a pass voltage is applied to the remaining word lines so that the memory cell is turned on irrespective of an erase state or a program state. A ground voltage of 0V is applied to the bit lines.
During the program operation, there exist memory cells in which an erase state (or a previous state) must be kept (hereinafter, referred to as “program-inhibited cells”). A program-inhibited voltage (for example, Vcc) is applied to the bit line BL2 connected to the string ST, including a program-inhibited cell (for example, Cb) in which a previous state must be kept without being programmed. If a program voltage is applied to the word line WLk after the channel region of the program-inhibited cell Cb is precharged to the program-inhibited voltage, the voltage of the channel region rises due to channel boosting. Accordingly, a program operation is not performed because a voltage difference between the channel region of the program-inhibited cell Cb and the word line WLk is low.
A program method of storing 2-bit data in one memory cell has recently been used. An erase operation of a memory cell block is performed anterior to a program operation, so that the entire memory cells become an erase state. Thus, the memory cells generally have 11 data stored therein. The program method for storing 2-bit data is performed by several program operations. Each program operation includes a LSB program operation of changing lower bits of the 2-bit data comprised of 11 data into 0 and a MSB program operation of changing upper bits thereof into 0.
In general, after the LSB program operation and the MSB program operation are sequentially performed on a selected word line, they are performed on a next word line adjacent to the selected word line. However, due to an interference phenomenon occurring between memory cells in the program operation, the threshold voltage of a memory cell connected to the selected word line and the adjacent word line may be changed during the program operation of the selected word line. In order to minimize such change, the order of the LSB program operation and the MSB program operation may be changed.
FIG. 2 is a sectional view illustrating the occurrence of a disturbance phenomenon due to hot carriers in a program operation of a memory cell.
Referring to FIGS. 1 and 2, when the order of the LSB program operation and the MSB program operation is changed, memory cells Ca and Cc sharing word lines WLk−1 and WLk+1 near a selected word line WLk have already become a LSB state (a state where the LSB program operation has been performed) or a MSB state (a state where the MSB program operation has been performed) in a program operation of a memory cell Cb. Thus, in the program operation of the memory cell Cb, the neighboring memory cells Ca and Cc are turned off. Due to this, the channel region of the memory cell Cb is isolated from the channel regions of the memory cells Ca and Cc.
In this state, if a program operation of the memory cell Cb is performed by applying a high program voltage Vpgm to the word line WLk, a boosting phenomenon occurs in a channel region 202a of the memory cell Cb, so a voltage of the channel region 202a rises. As the voltage of the channel region 202a rises, a voltage difference between the word line WLk and the channel region 202a of the memory cell Cb is lowered, so that the memory cell Cb is not programmed.
However, if the program voltage Vpgm is applied, hot carriers are generated at the corners of junction regions 202b and 202c adjacent to the neighboring word lines WLk−1 and WLk+1. The hot carriers are injected into a floating gate of the memory cell Cb due to the high program voltage. Consequently, the threshold voltage of the memory cell Cb that should not be programmed rises and a program disturbance phenomenon of the memory cell Cb occurs.